As the integration density of integrated circuit memory devices continues to increase, more memory cells may be provided in a single integrated circuit memory device. The increased numbers of integrated circuit memory cells may be arranged in larger data patch widths by providing more input/output channels. Unfortunately, the increased number of input/output channels may make it difficult to test multiple integrated circuit memory devices simultaneously, due to the limitation on the number of input/output channels in integrated circuit memory test equipment. Accordingly, it is known to provide a reduced data path width by reducing the number of input/output channels during testing of integrated circuit memory devices, so that the number of integrated circuit memory devices that can be tested simultaneously may be increased.
FIG. 1 shows a conventional memory device tested by using a representative data input/output channel.
Referring to FIG. 1, the memory device includes an array of memory cells; four input/output channels I/Oi, I/Oj, I/Ok and I/Ol; four data output buffers DOUT BUF i, DOUT BUF j, DOUT BUF k and DOUT BUF l; four data input buffers DIN BUF i, DIN BUF j, DIN BUF k and DIN BUF l; a comparator COMP; a data input driver DINDRV; a read multiplexer RMUX activated by a control signal MDQE; and a write multiplexer WMUX activated by the control signal MDQE. It will be understood that groups of input/output channels, groups of data output buffers, groups of data input buffers, groups of data input drivers, groups of comparators, groups of data input drivers, groups of read multiplexers and groups of write multiplexers also may be provided, as shown in FIG. 1. In a normal mode, the memory device inputs or outputs data via all of the four data input/output channel groups I/Oi, I/Oj, I/Ok and I/Ol.
Operation of the memory device in a test mode will now be described. First, while the control signal MDQE is active, the data is input via a representative data input/output channel group e.g., ith data input/output channel group I/Oi, and then buffered by the ith data input buffer group DIN BUF I to be input to the write multiplexer group WMUX via the ith data line DIi. The data output from the write multiplexer group WMUX is input to the data input driver group DINDRV, and the data output from the data input driver group DINDRV is simultaneously loaded onto the data input/output lines DIOi, DIOj, DIOk and DIOl to be stored in memory cells.
Also, the data stored in the memory cells are input to the comparator group COMP via the data input/output lines DIOi, DIOj, DIOk and DIOl, and comparison data FCOM output from the comparator group COMP is output to external of the memory device, via the read multiplexers RMUX, the ith data output buffer group DOUT BUF I, and the ith data input/output channel group I/Oi in sequence. Thus, in a conventional memory device, data is input or output via only one data input/output channel group in a test mode.
FIG. 2 is a circuit diagram of one of the read multiplexers RMUX shown in FIG. 1. Referring to FIG. 2, the read multiplexer RMUX includes a first buffering portion 11 for buffering data loaded on the data input/output lines DIOi, DIOj, DIOk and DIOl, a first selection portion 12 for selecting the comparison data FCOM output from the comparator group COMP (see FIG. 1) or the data buffered by the first buffering portion 11, and a first latch portion 13 for latching the data selected by the first selection portion 12.
The first buffering portion 11 includes inverters 111 and 112,121 and 122, 131 and 132, and 141 and 142 which are serially connected to the data input/output lines DIOi, DIOj, DIOk and DIOl, respectively. The first latch portion 13 includes inverters 114 through 116, 124 through 126, 134 through 136, and 144 through 146 which respectively latch the data loaded on the data input/output lines DIOi, DIOj, DIOk and DIOl.
The first selection portion 12 includes a first controller 101, a first switch 102 and a second switch 103. The first controller 101 switches on the first switch 102 or the second switch 103, and includes a first NAND gate 104, an inverter 105 and a second NAND gate 106. The first NAND gate 104 receives a read multiplexer enable signal RMUXE which is activated to a logic high when the read multiplexer RMUX is enabled, and the control signal MDQE. The inverter 105 inverts the control signal MDQE, and the second NAND gate 106 receives the signal output from the inverter 105 and the read multiplexer enable signal RMUXE.
The first switch 102 transmits the comparison data FCOM to the first latch portion 13 when activated by the signal output from the first NAND gate 104. The first switch 102 includes an inverter 109 for inverting the signal output from the first NAND gate 104, and a transmission gate 108. The transmission gate 108 has one end for receiving the signal output from the first NAND gate 104 and the other end for receiving the signal output from the inverter 109.
The second switch 103 transmits the data output from the first buffering portion 11 to the first latch portion 13 when activated by the signal output from the second NAND gate 106. The second switch 103 includes an inverter 110 for inverting the signal output from the second NAND gate 106, and a plurality of transmission gates 113, 123, 133 and 143 which respectively have one end to which the signal output from the second NAND gate 106 is input and the other end to which the signal output from the inverter 108 is input.
In a normal mode, the control signal MDQE is a logic low, and the read multiplexer enable signal RMUXE is a logic high, so that the first switch 102 is switched off, and the second switch 103 is switched on. Thus, the data loaded on the data input/output lines DIOi, DIOj, DIOk and DIOl are loaded onto data buses DBi, DBj, DBk and DBj via the first buffering portion 11 and the first latch portion 13 in sequence, and then buffered in the data output buffers DOUT BUF I, DOUT BUF j, DOUT BUF k and DOUT BUF l (see FIG. 1), and then output external of the memory device via the data input/output channel groups I/Oi, I/Oj, I/Ok and I/Ol (see FIG. 1).
In a test mode, the control signal MDQE is a logic high and the read multiplexer enable signal RMUXE is a logic low, so that the first switch 102 is switched on and the second switch 103 is switched off. As a result, the comparison data FCOM is loaded only onto the ith data bus DBi. The comparison data FCOM loaded onto the ith data bus DBi is input to the ith data output buffer DOUT BUF I (see FIG. 1) and output external of the memory device via only the ith data input/output channel group I/Oi (see FIG. 1).
FIG. 3 is a circuit diagram of one of write multiplexers WMUX of FIG. 1.
Referring to FIG. 3, the write multiplexer WMUX includes a second buffering portion 21 for buffering data loaded on the data lines DIi, DIj, DIk and DIl, a second selection portion 22 for selecting the data loaded on all the data lines DIi, DIj, DIk and DIl, or the data loaded onto one of data lines, e.g., ith data line DIi, among the data output from the second buffering portion 21, and a second latch portion 23 for latching the data selected by the second selection portion 22. The second buffering portion 21 includes inverters 151 and 152,161 and 162,171 and 172, and 181 and 182, and the second latch portion 23 includes inverters 155 through 157,165 through 167, 175 through 177, and 185 through 187. The second selection portion 22 includes a second controller 191, a third switch 192 and a fourth switch 193.
The second controller 191 activates the third switch 192 or the fourth switch 193, and includes an inverter 194, a NOR gate 195 and a third NAND gate 196. The inverter 194 inverts the write multiplexer enable signal WMUXE which is activated to a logic high when the write multiplexer WMUX becomes enabled. The NOR gate 195 receives the signal output from the inverter 194 and the control signal MDQE, and the third NAND gate 196 receives the write multiplexer enable signal WMUXE and the control signal MDQE.
The third switch 192 transmits the data loaded onto the data lines DIi, DIk, DIk and DIl to the second latch portion 23 when activated by the signal output from the NOR gate 195. The third switch 192 includes an inverter 198 for inverting the signal output from the NOR gate 195, and a plurality of transmission gates 153,163, 173 and 183 which respectively have one end for receiving the signal output from the NOR gate 195 and the other end for receiving the signal output from the inverter 198.
The fourth switch 193 transmits only the data loaded onto the ith data line DIi when being switched on by the signal output from the third NAND gate 196. The fourth switch 193 includes an inverter 197 for inverting the signal output from the third NAND gate 196, and a plurality of transmission gates 154,164,174 and 184 which respectively have one end for receiving the signal output from the third NAND gate 196 and the other end for receiving the signal output from the inverter 197.
The operation of the write multiplexer WMUX will now be described. First, in a normal mode where the control signal MDQE becomes disabled to a logic low, the third switch 192 is switched on and the fourth switch 193 is switched off, so that the data loaded onto the data lines DIi, DIj, DIk and DIl are loaded onto the data input/output lines DIOi, DIOj, DIOk and DIOl via the second buffering portion 21, the second latch portion 23 and a data input driver group (DINDRV) 24 in sequence, to be stored in the memory cells.
In a test mode where the control signal MDQE is active to logic high, the third switch 192 is switched off and the fourth switch 193 is switched on, so that only the data loaded onto the ith data line DIi is buffered by the second buffering portion 21 and then loaded onto the four data input/output lines DIOi, DIOj, DIOk and DIOl via the second latch portion 23. In other words, the data of the ith data line DIi is loaded onto all the data input/output lines DIOi, DIOj, DIOk and DIOl at the same time to be transmitted to the memory cells. Here, the data loaded onto the ith data line DIi is the data input via the ith data input/output channel group I/Oi.
As described above, in conventional memory devices, a representative data input/output channel group is fixed in a test mode. Thus, when the memory device is tested using test equipment having a limited number of data input/output channels, the reason for failure such as open, short and leakage current in the circuits related to the representative data input/output channel, such as data output buffer, data input buffer, read multiplexer and write multiplexer, may be found. However, the reason for the failure may not be found if the failure occurs in the circuits related to the remaining data input/output channels other than the representative data input/output channel.